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SI5341/40 rev d data sheet low-jitter, 10 or 4-output, any-frequency, any-output clock generator the any-frequency, any-output SI5341/40 clock generators combine a wide-band pll with proprietary multisynth ? fractional synthesizer technology to offer a versatile and high performance clock generator platform. this highly flexible architecture is capable of synthesizing a wide range of integer and non-integer related frequencies up to 1 ghz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter per- formance with 0 ppm error. each of the clock outputs can be assigned its own format and output voltage enabling the SI5341/40 to replace multiple clock ics and oscillators with a single device making it a true "clock tree on a chip." the SI5341/40 can be quickly and easily configured using clockbuilderpro software. custom part numbers are automatically assigned using a clockbuilder pro ? for fast, free, and easy factory pre-programming or the SI5341/40 can be programmed via i2c and spi serial interfaces. applications: ? clock tree generation replacing xos, buffers, signal format translators ? any-frequency clock translation ? clocking for fpgas, processors, memory ? ethernet switches/routers ? otn framers/mappers/processors ? test equipment and instrumentation ? broadcast video key features ? generates any combination of output frequencies from any input frequency ? ultra-low jitter of 90 fs rms ? input frequency range: ? external crystal: 25 to 54 mhz ? differential clock: 10 to 750 mhz ? lvcmos clock: 10 to 250 mhz ? output frequency range: ? differential: 100 hz to 1028 mhz ? lvcmos: 100 hz to 250 mhz ? highly configurable outputs compatible with lvds, lvpecl, lvcmos, cml, and hcsl with programmable signal amplitude ? SI5341: 4 input, 10 output, 64-qfn 9x9 mm ? si5340: 4 input, 4 output, 44-qfn 7x7 mm up to 10 output clocks out7 out6 out5 out1 out4 out3 out2 out0 si5340 SI5341 i2c / spi control nvm status flags status monitor 4 input clocks xb xa 25-54 mhz xtal osc multisynth int int int int int int int int multisynth multisynth multisynth multisynth int int int pll int out9 out8 int int in0 in1 in2 fb_in zero delay silabs.com | smart. connected. energy-friendly. rev. 1.0
1. features list the SI5341/40 rev d features are listed below: ? generates any combination of output frequencies from any in- put frequency ? ultra-low jitter of 90 fs rms ? input frequency range: ? external crystal: 25 to 54 mhz ? differential clock: 10 to 750 mhz ? lvcmos clock: 10 to 250 mhz ? output frequency range: ? differential: 100 hz to 1028 mhz ? lvcmos: 100 hz to 250 mhz ? highly configurable outputs compatible with lvds, lvpecl, lvcmos, cml, and hcsl with programmable signal ampli- tude ? locks to gapped clock inputs ? optional zero delay mode ? glitchless on the fly output frequency changes ? dco mode: as low as 0.001 ppb steps ? core voltage ? vdd: 1.8 v 5% ? vdda: 3.3 v 5% ? independent output clock supply pins ? 3.3 v, 2.5 v, or 1.8 v ? serial interface: i2c or spi ? in-circuit programmable with non-volatile otp memory ? clockbuilder pro software simplifies device configuration ? SI5341: 4 input, 10 output, 64-qfn 9x9 mm ? si5340: 4 input, 4 output, 44-qfn 7x7 mm ? temperature range: C40 to +85 c ? pb-free, rohs-6 compliant SI5341/40 rev d data sheet features list silabs.com | smart. connected. energy-friendly. rev. 1.0 | 1
2. ordering guide table 2.1. SI5341/40 ordering guide ordering part number (opn) number of in- put/output clocks output clock frequency range (mhz) frequency syn- thesis mode package temperature range SI5341 SI5341a-d-gm 1, 2 4/10 0.0001 to 1028 mhz integer and fractional 64-qfn 9x9 mm C40 to 85 c SI5341b-d-gm 1, 2 0.0001 to 350 mhz SI5341c-d-gm 1, 2 0.0001 to 1028 mhz integer only SI5341d-d-gm 1, 2 0.0001 to 350 mhz si5340 si5340a-d-gm 1 , 2 4/4 0.0001 to 1028 mhz integer and fractional 44-qfn 7x7 mm C40 to 85 c si5340b-d-gm 1, 2 0.0001 to 350 mhz si5340c-d-gm 1, 2 0.0001 to 1028 mhz integer only si5340d-d-gm 1, 2 0.0001 to 350 mhz SI5341/40-d-evb SI5341-d-evb evaluation board si5340-d-evb note: 1. add an r at the end of the opn to denote tape and reel ordering options. 2. custom, factory pre-programmed devices are available. ordering part numbers are assigned by silicon labs and the clockbuild- er pro software utility. custom part number format is: e.g., SI5341a-dxxxxx-gm, where "xxxxx" is a unique numerical sequence representing the preprogrammed configuration. 3. see 3.9 custom factory preprogrammed devices and 3.10 enabling features and/or configuration settings not available in clockbuilder pro for factory pre-programmed devices for important notes about specifying a preprogrammed device to use fea- tures or device register settings not yet available in cbpro. SI5341/40 rev d data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 1.0 | 2
si534fg-rxxxxx-gm timing product family f = multi-pll clock f amily member (7, 6) g = device g rade (a, b, c, d) product r evision* custom ordering part number (opn) sequence id** package, ambient temperature range (qfn, -40 c to +85c) *see ordering guide table for current product revision ** 5 digits; assigned by clockbuilder pro figure 2.1. ordering part number fields SI5341/40 rev d data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 1.0 | 3
3. functional description the si5340/41-d combines a wide band pll with next generation multisynth technology to offer the industry's most versatile and high performance clock generator. the pll locks to either an external crystal between xa/xb or to an external clock connected to xa/xb or in0, 1, 2. a fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is then divided by the multisynth output stage to any frequency in the range of 100 hz to 1 ghz on each output. the multisynth stage can divide by both integer and fractional values. the high-resolution fractional multisynth dividers enable true any-frequency input to any- frequency on any of the outputs. the output drivers offer flexible output formats which are independently configurable on each of the outputs. this clock generator is fully configurable via its serial interface (i 2 c/spi) and includes in-circuit programmable non-volatile memory. 3.1 power-up and initialization once power is applied, the device begins an initialization period where it downloads default register values and configuration data from nvm and performs other initialization tasks. communicating with the device through the serial interface is possible once this initializa- tion period is complete. no clocks will be generated until the initialization is done. there are two types of resets available. a hard reset is functionally similar to a device power-up. all registers will be restored to the values stored in nvm, and all circuits will be restored to their initial state including the serial interface. a hard reset is initiated using the rstb pin or by asserting the hard reset bit. a soft reset bypasses the nvm download. it is simply used to initiate register configuration changes. power-up serial interface ready rstb pin asserted hard reset bit asserted initialization nvm download soft reset bit asserted figure 3.1. SI5341 power-up and initialization 3.2 frequency configuration the phase-locked loop is fully contained and does not require external loop filter components to operate. its function is to phase lock to the selected input and provide a common reference to the multisynth high-performance fractional dividers. a crosspoint mux connects any of the multisynth divided frequencies to any of the outputs drivers. additional output integer dividers provide further frequency division by an even integer from 2 to (2^25)-2. the frequency configuration of the device is programmed by setting the input dividers (p), the pll feedback fractional divider (mn/md), the multisynth fractional dividers (nn/nd), and the output integer dividers (r). silicon labs's clockbuilder pro configuration utility determines the optimum divider values for any desired input and output frequency plan. 3.3 inputs the si5340/41-d requires either an external crystal at its xa/xb pins or an external clock at xa/xb or in0, 1, 2. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 4
3.3.1 xa/xb clock and crystal input an internal crystal oscillator exists between pin xa and xb. when this oscillator is enabled, an external crystal connected across these pins will oscillate and provide a clock input to the pll. a crystal frequency of 25 mhz can be used although crystals in the frequency range of 48 mhz to 54 mhz are recommended for best jitter performance. frequency offsets due to c l mismatch can be adjusted using the frequency adjustment feature which allows frequency adjustments of 1000 ppm. the si5340/41 family reference manual pro- vides additional information on pcb layout recommendations for the crystal to ensure optimum jitter performance. refer to table 5.12 crystal specifications on page 31 for crystal specifications. to achieve optimal jitter performance and minimize bom cost, a crystal is recommended on the xa/xb reference input. a clock (e.g., xo) may be used in lieu of the crystal, but it will result in higher output jitter. see the si5340/41 reference manual for more information. selection between the external xtal or input clock is controlled by register configuration. the internal crystal load capacitors (c l ) are disabled in the input clock mode. refer to table 5.3 input clock specifications on page 20 for the input clock requirements at xaxb. both a single-ended or a differential input clock can be connected to the xa/xb pins as shown in the figure below. a p xaxb divider is available to accommodate external clock frequencies higher than 54 mhz. 100 differential connection 2xc l 2xc l xb xa 2xc l 2xc l xb xa single- ended xo connection crystal connection osc xb xa xtal 2xc l 2xcl SI5341/40 SI5341/40 SI5341/40 note: 2. 0 vpp_ se max xo with clipped sine wave output 2xc l 2xc l xb xa osc SI5341/40 note: 2. 0 vpp_ se max cmos output r2 r1 xo vdd r 1 r2 3. 3 v 523 ohms 442 ohms 2. 5 v 475 ohms 649 ohms 1. 8 v 158 ohms 866 ohms 100 0. 1 uf 0. 1 uf 0. 1 uf 0. 1 uf 0. 1 uf 0. 1 uf 0. 1 uf single-ended connection note: 2. 5 vpp diff max x1 x2 nc nc x1 x2 nc nc x1 x2 nc nc x2 x1 osc osc figure 3.2. xaxb external crystal and clock connections SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 5
3.3.2 input clocks (in0, in1, in2) a differential or single-ended clock can be applied at in2, in1, or in0. the recommended input termination schemes are shown in the figure below. pulsed cmos dc coupled single ended standard ac coupled single ended 100 3.3v, 2.5v, 1.8v l vcmos standard ac coupled differential lvpecl inx inxb 50 100 standard ac coupled differential lvds inx inxb 3.3v , 2.5v l vpecl 3.3v , 2.5v l vds or cml inx inxb inx inxb 50 50 50 50 pulsed cmos standard SI5341/40 SI5341/40 SI5341/40 SI5341/40 3.3v , 2.5v, 1.8v l vcmos 50 r 2 r1 pulsed cmos standard pulsed cmos standard pulsed cmos standard vdd r1 (ohm) r2 (ohm) 1.8 v 2.5 v 3.3 v 324 51 1 634 665 475 365 figure 3.3. termination of differential and lvcmos input signals SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 6
3.3.3 input selection (in0, in1, in2, xa/xb) the active clock input is selected using the in_sel[1:0] pins or by register control. a register bit determines input selection as pin or register selectable. there are internal pull ups on the in_sel pins. table 3.1. manual input selection using in_sel[1:0] pins in_sel[1:0] selected input 0 0 in0 0 1 in1 1 0 in2 1 1 xa/xb 3.4 fault monitoring the si5340/41-d provides fault indicators which monitor loss of signal (los) of the inputs (in0, in1, in2, xa/xb, fb_in) and loss of lock (lol) for the pll as shown in the figure below. pll lpf pd mn in0 in0b los0 p 0 in1 in1b p 1 fb_in fb _inb in2 in2b p 2 lol SI5341/40 xb xa osc p fb md losxab los1 los2 lolb losxab intrb losfb (si5340) figure 3.4. los and lol fault monitors 3.4.1 status indicators the state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (lolb). each of the status indicator register bits has a corresponding sticky bit in a separate register location. once a status bit is asserted its corre- sponding sticky bit (_flg) will remain asserted until cleared. writing a logic zero to a sticky register bit clears its state. 3.4.2 interrupt pin (intrb) an interrupt pin (intrb) indicates a change in state with any of the status registers. all status registers are maskable to prevent asser- tion of the interrupt pin. the state of the intrb pin is reset by clearing the status registers. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 7
3.5 outputs the SI5341 supports 10 differential output drivers which can be independently configured as differential or lvcmos. the si5340 sup- ports 4 output drivers independently configurable as differential or lvcmos. 3.5.1 output signal format the differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal formats including lvds and lvpecl. in addition to supporting differential signals, any of the outputs can be configured as lvcmos (3.3 v, 2.5 v, or 1.8 v) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. 3.5.2 differential output terminations the differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below. 100 50 50 internally self-biased ac coupled lvds/lvpecl 50 50 ac coupled lvpecl /cml vdd C 1.3v 50 50 50 50 100 dc coupled lvds outx outxb outx outxb outx outxb v ddo = 3.3v , 2.5v , 1.8v v ddo = 3.3v , 2.5v v ddo = 3.3v , 2.5v , 1.8v si 5341/40 si 5341/40 si 5341/40 ac coupled hcsl r1 outx outxb v ddo = 3.3v, 2.5v, 1.8v SI5341/40 50 50 r1 r2 r2 vdd rx standard hcsl receiver vdd rx option 1 for v cm = 0. 37 v 3. 3 v 2. 5 v 1. 8 v 442 ohms 332 ohms 243 ohms 56.2 ohms 59 ohms 63.4 ohms r1 r2 figure 3.5. supported differential output terminations 3.5.3 programmable common mode voltage for differential outputs the common mode voltage (vcm) for the differential modes are programmable so that lvds specifications can be met and for the best signal integrity with different supply voltages. when dc coupling the output driver it is essential that the receiver should have a relatively high common mode impedance so that the common mode current from the output driver is very small. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 8
3.5.4 lvcmos output terminations lvcmos outputs are typically dc-coupled, as shown in the figure below. 3.3v , 2.5v , 1.8 v lvcmos v ddo = 3.3v , 2.5v , 1.8v 50 rs 50 rs dc coupled lvcmos outx outxb figure 3.6. lvcmos output terminations 3.5.5 lvcmos output impedance and drive strength selection each lvcmos driver has a configurable output impedance. it is highly recommended that the minimum output impedance (strongest drive setting) is selected and a suitable series resistor (rs) is chosen to match the trace impedance. table 3.2. nominal output impedance vs. outx_cmos_drv (register) vddo cmos_drive_selection outx_cmos_drv=1 outx_cmos_drv=2 outx_cmos_drv=3 3.3 v 38 30 22 2.5 v 43 35 24 1.8 v 46 31 note: refer to the si5340/41 family reference manual for more information on register settings. 3.5.6 lvcmos output signal swing the signal swing (v ol /v oh ) of the lvcmos output drivers is set by the voltage on the vddo pins. each output driver has its own vddo pin allowing a unique output voltage swing for each of the lvcmos drivers. 3.5.7 lvcmos output polarity when a driver is configured as an lvcmos output it generates a clock signal on both pins (outx and outxb). by default the clock on the outxb pin is generated with complementary polarity with the clock on the outx pin. the lvcmos outx and outxb outputs can also be generated in phase. 3.5.8 output enable/disable the oeb pin provides a convenient method of disabling or enabling the output drivers. when the oeb pin is held high all outputs will be disabled. when held low, the outputs will be enabled. outputs in the enabled state can be individually disabled through register control. 3.5.9 output driver state when disabled the disabled state of an output driver is configurable as: disable low or disable high. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 9
3.5.10 synchronous/asynchronous output disable feature outputs can be configured to disable synchronously or asynchronously. the default state is synchronous output disable. in synchro- nous disable mode the output will wait until a clock period has completed before the driver is disabled. this prevents unwanted runt pulses from occurring when disabling an output. in asynchronous disable mode the output clock will disable immediately without waiting for the period to complete. 3.5.11 output delay control ( t 0 - t 4 ) the SI5341/40 uses independent multisynth dividers (n 0 - n 4 ) to generate up to 5 unique frequencies to its 10 outputs through a cross- point switch. by default all clocks are phase aligned. a delay path ( t0 - t4) associated with each of these dividers is available for applica- tions that need a specific output skew configuration. each delay path is controlled by a register parameter call nx_delay with a resolu- tion of ~0.28 ps over a range of ~9.14 ns. this is useful for pcb trace length mismatch compensation. after the delay controls are configured, the soft reset bit soft_rst must be set high so that the output delay takes effect and the outputs are re-aligned. n 0 t 0 n 1 t 1 n 2 t 2 n 3 t 3 n 4 t 4 out2b vddo2 out2 vddo3 r 2 out3b out3 r 3 out1b vddo1 out1 r 1 out5b vddo5 out5 vddo6 r 5 out6b out6 r 6 out4b vddo4 out4 r 4 out7b vddo7 out7 vddo8 r 7 out8b out8 r 8 out0b vddo0 out0 r 0 vddo9 out9b out9 r 9 figure 3.7. example of independently configurable path delays all delay values are restored to their nvm programmed values after power-up or after a hard reset. delay default values can be written to the nvm allowing a custom delay offset configuration at power-up or after a hardware reset. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 10
3.5.12 zero delay mode a zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. the zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in the figure below. this helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. any one of the outputs can be fed back to the fb_in pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. it is recommended to connect out9 (SI5341) or out3 (si5340) to fb_in for external feedback. the fb_in input pins must be terminated and ac-coupled when zero delay mode is used. a differential external feedback path connection is necessary for best performance. zero delay mode SI5341 in_ sel[1:0] in0 in0b in1 in1b in2 in2b p 0 p 1 p 2 out0b vddo0 out0 out2b vddo2 out2 out3b vddo3 out3 out7b vddo7 out7 out8b vddo8 out8 out9b vddo9 out9 out1b vddo1 out1 multisynth & dividers fb_in fb_inb 100 external feedback path pd lpf m n m d n 9n n 9d r 9 f fb = f in f in p fb pll figure 3.8. SI5341 zero delay mode setup 3.5.13 sync pin (synchronizing r dividers) all the output r dividers are reset to the default nvm register state after a power-up or a hard reset. this ensures consistent and re- peatable phase alignment across all output drivers to within 100 ps of the expected value from the nvm download. resetting the de- vice using the rstb pin or asserting the hard reset bit will have the same result. the syncb pin provides another method of re-aligning the r dividers without resetting the device, however, the outputs will only align to within 50 ns when using the syncb pin. this pin is positive edge triggered. asserting the sync register bit provides the same function as the syncb pin. a soft reset will align the outputs to within 100 ps of the expected value based upon the nx_delay parameter. 3.5.14 output crosspoint the output crosspoint allows any of the n dividers to connect to any of the clock outputs. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 11
3.5.15 digitally controlled oscillator (dco) modes each multisynth can be digitally controlled so that all outputs connected to the multisynth change frequency in real time without any transition glitches. there are two ways to control the multisynth to accomplish this task: ? use the frequency increment/decrement pins or register bits. ? write directly to the numerator of the multisynth divider. an output that is controlled as a dco is useful for simple tasks such as frequency margining or cpu speed control. the output can also be used for more sophisticated tasks such as fifo management by adjusting the frequency of the read or write clock to the fifo or using the output as a variable local oscillator in a radio application. 3.5.15.1 dco with frequency increment/decrement pins/bits each of the multisynth fractional dividers can be independently stepped up or down in predefined steps with a resolution as low as 0.001 ppb. setting of the step size and control of the frequency increment or decrement is accomplished by setting the step size with the 44 bit frequency step word (fstepw). when the finc or fdec pin or register bit is asserted the output frequency will increment or decrement respectively by the amount specified in the fstepw. 3.5.15.2 dco with direct register writes when a multisynth numerator and its corresponding update bit is written, the new numerator value will take effect and the output fre- quency will change without any glitches. the multisynth numerator and denominator terms can be left and right shifted so that the least significant bit of the numerator word represents the exact step resolution that is needed for your application. 3.6 power management several unused functions can be powered down to minimize power consumption. consult the si5340/41 family reference manual and clockbuilder pro configuration utility for details. 3.7 in-circuit programming the SI5341/40 is fully configurable using the serial interface (i 2 c or spi). at power-up the device downloads its default register values from internal non-volatile memory (nvm). application specific default configurations can be written into nvm allowing the device to gen- erate specific clock frequencies at power-up. writing default values to nvm is in-circuit programmable with normal operating power sup- ply voltages applied to its v dd and v dda pins. the nvm is two time writable. once a new configuration has been written to nvm, the old configuration is no longer accessible. refer to the si5340/41 family reference manual for a detailed procedure for writing registers to nvm. 3.8 serial interface configuration and operation of the SI5341/40 is controlled by reading and writing registers using the i 2 c or spi interface. the i2c_sel pin selects i 2 c or spi operation. communication with both 3.3 v and 1.8 v host is supported. the spi mode operates in either 4-wire or 3-wire. see the si5340/41 family reference manual for details. 3.9 custom factory preprogrammed devices for applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into nvm. a factory pre-programmed device will generate clocks at power-up. custom, factory-pre- programmed devices are available. use the clockbuilder pro custom part number wizard ( www.silabs.com/clockbuilderpro ) to quickly and easily request and generate a custom part number for your configuration. in less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your designs configuration. once you receive the confirmation email with the data sheet addendum, simply place an order with your local silicon labs sales representative. samples of your pre-pro- grammed device will ship to you typically within two weeks. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 12
3.10 enabling features and/or configuration settings not available in clockbuilder pro for factory pre-programmed devices as with essentially all software utilities, clockbuilder pro is continuously updated and enhanced. by registering at http:// www.silabs.com and opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes are. this update process will ultimately enable clockbuilder pro users to access all features and register setting values docu- mented in this data sheet and the SI5341/40 family reference manual . however, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in cbpro, you must contact a silicon labs applications engineer for assistance. an example of this type of feature or custom setting is the customizable amplitudes for the clock outputs. after careful review of your project file and custom requirements, a silicon labs applica- tions engineer will email back your cbpro project file with your specific features and register settings enabled, using what is referred to as the manual "settings override" feature of cbpro. "override" settings to match your request(s) will be listed in your design report file. examples of setting "overrides" in a cbpro design report are shown below: table 3.3. setting overrides location name type target dec value hex value 0128[6:4] out6_ampl user opn & evb 5 5 once you receive the updated design file, simply open it in cbpro. after you create a custom opn, the device will begin operation after startup with the values in the nvm file, including the silicon labs-supplied override settings. SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 13
do i need a pre-programmed device with a feature or setting which is unavailable in clockbuilder pro? no yes contact silicon labs technical support to submit & review your non-standard configuration request & cbpro project file configure device using cbpro load project file into cbpro and test receive updated cbpro project file from silicon labs with settings override generate custom opn in cbpro does the updated cbpro project file match your requirements? yes end: place sample order start figure 3.9. flowchart to order custom parts with features not available in cbpro note: contact silicon labs technical support at www.silabs.com/support/pages/default.aspx . SI5341/40 rev d data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 14
4. register map the register map is divided into multiple pages where each page has 256 addressable registers. page 0 contains frequently accessible registers such as alarm status, resets, device identification, etc. other pages contain registers that need less frequent access such as frequency configuration, and general device settings. a high level map of the registers is shown in 4.2 high-level register map . refer to the si5340/41 family reference manual for a complete list of register descriptions and settings. 4.1 addressing scheme the device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register address. by default the page address is set to 0x00. changing to another page is accomplished by writing to the set page address byte located at ad- dress 0x01 of each page. SI5341/40 rev d data sheet register map silabs.com | smart. connected. energy-friendly. rev. 1.0 | 15
4.2 high-level register map table 4.1. high-level register map 16-bit address content 8-bit page address 8-bit register address range 00 00 revision ids 01 set page address 02-0a device ids 0b-15 alarm status 17-1b intr masks 1c reset controls 2c-e1 alarm configuration e2-e4 nvm controls fe device ready status 01 01 set page address 08-3a output driver controls 41-42 output driver disable masks fe device ready status 02 01 set page address 02-05 xtal frequency adjust 08-2f input divider (p) settings 30 input divider (p) update bits 35-3d pll feedback divider (m) settings 3e pll feedback divider (m) update bit 47-6a output divider (r) settings 6b-72 user scratch pad memory fe device ready status 03 01 set page address 02-37 multisynth divider (n0-n4) settings 0c multisynth divider (n0) update bit 17 multisynth divider (n1) update bit 22 multisynth divider (n2) update bit 2d multisynth divider (n3) update bit 38 multisynth divider (n4) update bit 39-58 finc/fdec settings n0-n4 59-62 output delay (dt) settings 63-94 frequency readback n0-n4 fe device ready status SI5341/40 rev d data sheet register map silabs.com | smart. connected. energy-friendly. rev. 1.0 | 16
16-bit address content 8-bit page address 8-bit register address range 04-08 00-ff reserved 09 01 set page address 49 input settings 1c zero delay mode settings a0-ff 00-ff reserved SI5341/40 rev d data sheet register map silabs.com | smart. connected. energy-friendly. rev. 1.0 | 17
5. electrical specifications table 5.1. recommended operating conditions 1 (v dd =1.8 v 5%, v dda =3.3 v 5%, t a = C40 to 85c) parameter symbol min typ max units ambient temperature t a C40 25 85 c junction temperature tj max 125 c core supply voltage v dd 1.71 1.80 1.89 v v dda 3.14 3.30 3.47 v output driver supply voltage v ddo 3.14 3.30 3.47 v 2.37 2.50 2.62 v 1.71 1.80 1.89 v note: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical val- ues apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 18
table 5.2. dc characteristics (v dd =1.8v 5%, v dda =3.3v 5%, v ddo =1.8v 5%, 2.5v 5%, or 3.3v 5%, t a = -40 to 85c) parameter symbol test condition min typ max units core supply current 1, 2 i dd si5340/41 115 230 ma i dda si5340/41 120 130 ma output buffer supply current i ddox lvpecl output 3 @ 156.25 mhz 22 26 ma lvds output 3 @ 156.25 mhz 15 18 ma 3.3 v lvcmos 4 output @ 156.25 mhz 22 30 ma 2.5 v lvcmos 4 output @ 156.25 mhz 18 23 ma 1.8 v lvcmos 4 output @ 156.25 mhz 12 16 ma total power dissipation 1, 5 p d SI5341 880 1150 mw si5340 680 875 mw note: 1. SI5341 test configuration: 7 x 2.5 v lvds outputs enabled @ 156.25 mhz. excludes power in termination resistors. 2. si5340 test configuration: 4 x 2.5 v lvds outputs enabled @ 156.25 mhz. excludes power in termination resistors. 3. differential outputs terminated into an ac-coupled 100 ? load. 4. lvcmos outputs measured into a 6-inch 50 w pcb trace with 5 pf load. the lvcmos outputs were set to outx_cmos_drv=3, which is the strongest driver setting. refer to the SI5341/40 family reference manual for more details on register settings. 50 50 100 out outb i ddo differential output test configuration 0. 1 uf 0. 1 uf 50 outa i ddo 5 pf lvcmos output test configuration 6 inch outb 5. detailed power consumption for any configuration can be estimated using clockbuilderpro when an evaluation board (evb) is not available. all evbs support detailed current measurements for any configuration. SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 19
table 5.3. input clock specifications (v dd =1.8v 5%, v dda =3.3v 5%, t a =-40 to 85c) parameter symbol test condition min typ max units standard input buffer with differential or single-ended - ac-coupled (in0/in0b, in1/in1b, in2/in2b, fb_in/fb_inb) input frequency range f in differential 0.008 750 mhz all single-ended signals (including lvcmos) 0.008 250 mhz input voltage swing 1 v in differential ac-coupled f in < 250 mhz 100 1800 mvpp_se differential ac-coupled 250 mhz < f in < 750 mhz 225 1800 mvpp_se single-ended ac-coupled f in < 250 mhz 100 3600 mvpp_se slew rate 2, 3 sr 400 v/s duty cycle dc 40 60 % input capacitance c in 0.3 pf input resistance r in 16 k? pulsed cmos input buffer - dc coupled (in0, in1, in2) 4 input frequency f in 0.008 250 mhz input voltage v il C0.2 0.4 v v ih 0.8 v slew rate 2, 3 sr 400 v/s duty cycle dc clock input 40 60 % minimum pulse width pw pulse input 1.6 ns input resistance r in 8 k? refclk (applied to xa/xb) input frequency range f in full operating range. jitter performance may be re- duced. 10 200 mhz range for best jitter. 48 54 mhz input single-ended voltage swing v in_se 365 2000 mvpp_se input differential voltage swing v in_diff 365 2500 mvpp_diff slew rate 2, 3 sr imposed for best jitter per- formance 400 v/s input duty cycle dc 40 60 % SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 20
parameter symbol test condition min typ max units note: 1. voltage swing is specified as single-ended mvpp. vpp_se vpp_se vpp_diff = 2*vpp_se vcm vcm 2. imposed for jitter performance. 3. pulsed cmos mode is intended primarily for single-ended lvcmos input clocks < 1 mhz, which must be dc-coupled because they have a duty cycle significantly less than 50%. a typical application example is a low frequency video frame sync pulse. since the input thresholds (v il , v ih ) of this buffer are non-standard (0.4 and 0.8 v, respectively), refer to the input attenuator circuit for dc-coupled pulsed lvcmos in the family reference manual . otherwise, for standard lvcmos input clocks, use the standard ac-coupled, single-ended input mode. 4. dc-coupled cmos input buffer selection is not supported in clockbuilder pro for new designs. for single-ended lvcmos inputs to in0,1,2 it is required to ac-couple into the differential input buffer. table 5.4. control input pin specifications (v dd =1.8v 5%, v dda =3.3v 5%, v dds =3.3v 5%, 1.8v 5%, t a =-40 to 85c) parameter symbol test condition min typ max units SI5341 control input pins (i2c_sel, in_sel[1:0], rstb, oeb, syncb, a1, sclk, a0/csb, finc, fdec, sda/sdio) input voltage v il 0.3xv ddio 1 v v ih 0.7xv ddio 1 v input capacitance c in 2 pf input resistance r in 20 kw minimum pulse width t pw rstb, syncb, finc, and fdec 100 ns frequency update rate f ur finc and fdec 1 mhz si5340 control input pins (i2c_sel, in_sel[1:0], rstb, oeb, a1, sclk, a0/csb, sda/sdio) input voltage v il 0.3xv ddio 1 v v ih 0.7xv ddio 1 v input capacitance c in 2 pf input resistance r in 20 kw minimum pulse width t pw rstb only 100 ns note: 1. v ddio is determined by the io_vdd_sel bit. it is selectable as v dda or v dd . refer to the family reference manual for more details on register settings. SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 21
table 5.5. differential clock output specifications (v dd =1.8 v 5%, v dda =3.3v 5%, v ddo =1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = -40 to 85c) parameter symbol test condition min typ max units output frequency f out multisynth not used 0.0001 720 mhz 733.33 800.00 825 1028 multisynth used 0.0001 720 mhz duty cycle dc f out < 400 mhz 48 52 % 400 mhz < f out < 1028 mhz 45 55 % output-output skew using same multisynth t sks outputs on same multisynth (measured at 712.5 mhz) 65 ps output-output skew between multisynths t skd outputs from different multisynths (measured at 712.5 mhz) 90 ps out-outb skew t sk_out measured from the positive to negative output pins 0 50 ps output voltage swing 1 v out lvds 350 430 510 mvpp_se lvpecl 640 750 900 common mode voltage 1, 2 v cm v ddo = 3.3 v lvds 1.10 1.2 1.3 v lvpecl 1.90 2.0 2.1 v ddo = 2.5 v lvpecl lvds 1.1 1.2 1.3 v ddo = 1.8 v sub-lvds 0.8 0.9 1.0 rise and fall times (20% to 80%) t r /t f 100 150 ps differential output impedance z o 100 power supply noise rejection 2 psrr 10 khz sinusoidal noise C101 dbc 100 khz sinusoidal noise C96 500 khz sinusoidal noise C99 1 mhz sinusoidal noise C97 output-output crosstalk 3 xtalk SI5341 C72 dbc si5340 C88 dbc SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 22
parameter symbol test condition min typ max units notes: 1. output amplitude and common-mode settings are programmable through register settings and can be stored in nvm. each out- put driver can be programmed independently. the maximum lvds single-ended amplitude can be up to 110 mv higher than the tia/eia-644 maximum. refer to the SI5341/40 family reference manual for more suggested output settings. not all combina- tions of voltage amplitude and common mode voltages settings are possible. outxb outx vpp_se vpp_se vpp_ diff = 2* vpp_se vcm vcm 2. measured for 156.25 mhz carrier frequency. 100 mvpp sinewave noise added to vddo = 3.3 v and noise spur amplitude meas- ured. 3. measured across two adjacent outputs, both in lvds mode, with the victim running at 155.52 mhz and the aggressor at 156.25 mhz. refer to application note, an862: optimizing si534x jitter performance in next generation internet infrastructure systems, guidance on crosstalk minimization. table 5.6. lvcmos clock output specifications (v dd =1.8v 5%, v dda =3.3v 5%, v ddo =1.8v 5%, 2.5v 5%, or 3.3v 5%, t a = -40 to 85c) parameter symbol test condition min typ max units output frequency 0.0001 250 mhz duty cycle dc f out < 100 mhz 48 52 % 100 mhz < f out < 250 mhz 45 55 output-to-output skew t sk outputs on same multisynth. f out = 156.25 mhz 30 140 ps output voltage high 1, 2 , 3 v oh v ddo = 3.3 v outx_cmos_drv=1 i oh = -10 ma v ddo x 0.85 v outx_cmos_drv=2 i oh = -12 ma outx_cmos_drv=3 i oh = -17 ma v ddo = 2.5 v outx_cmos_drv=1 i oh = -6 ma v ddo x 0.85 v outx_cmos_drv=2 i oh = -8 ma outx_cmos_drv=3 i oh = -11 ma v ddo = 1.8 v outx_cmos_drv=2 i oh = -4 ma v ddo x 0.85 v outx_cmos_drv=3 i oh = -5 ma SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 23
parameter symbol test condition min typ max units output voltage low 1, 2, 3 v ol v ddo = 3.3 v outx_cmos_drv=1 i ol = 10 ma v ddo x 0.15 v outx_cmos_drv=2 i ol = 12 ma outx_cmos_drv=3 i ol = 17 ma v ddo = 2.5 v outx_cmos_drv=1 i ol = 6 ma v ddo x 0.15 v outx_cmos_drv=2 i ol = 8 ma outx_cmos_drv=3 i ol = 11 ma v ddo = 1.8 v outx_cmos_drv=2 i ol = 4 ma v ddo x 0.15 v outx_cmos_drv=3 i ol = 5 ma lvcmos rise and fall times 3 (20% to 80%) tr/tf vddo = 3.3v 400 600 ps vddo = 2.5 v 450 600 ps vddo = 1.8 v 550 750 ps notes: 1. driver strength is a register programmable setting and stored in nvm. options are outx_cmos_drv = 1, 2, 3. refer to the family reference manual for more details on register settings. 2. i ol /i oh is measured at v ol /v oh as shown in the dc test configuration. 3. a series termination resistor (rs) is recommended to help match the source impedance to a 50 w pcb trace. a 5 pf capacitive load is assumed. the lvcmos outputs were set to outx_cmos_drv = 3. zs i ol /i oh v ol /v oh 50 out outb i ddo trace length 5 inches 50 4.7 pf 4.7 pf 56 499 499 56 ac test configuration 50 probe, scope 50 probe, scope dc block dc block dc test configuration SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 24
table 5.7. output status pin specifications (v dd =1.8v 5%, v dda =3.3v 5%, v dds = 3.3v 5%, 1.8v 5%, t a = -40 to 85c) parameter symbol test condition min typ max units SI5341/40 status output pins (intrb, sda/sdio) 1 output voltage v oh i oh = -2 ma v ddio 2 x 0.85 v v ol i ol = 2 ma v ddio 2 x 0.15 v SI5341 status output pins (lolb) output voltage v oh i oh = -2 ma v ddio 2 x 0.85 v v ol i ol = 2 ma v ddio 2 x 0.15 v si5340 status output pins (lolb, los_xaxbb) output voltage v oh i oh = -2 ma v dds x 0.85 v v ol i ol = 2 ma v dds x 0.15 v notes: 1. the v oh specification does not apply to the open-drain sda/sdio output when the serial interface is in i2c mode or is unused with i2c_sel pulled high. v ol remains valid in all cases. 2. v ddio is determined by the io_vdd_sel bit. it is selectable as v dda or v dd . refer to the family reference manual for more details on register settings. table 5.8. performance characteristics (v dd =1.8v 5%, v dda =3.3v 5%, t a = -40 to 85c) parameter symbol test condition min typ max units v co frequency range f vco 13.5 14.4 ghz pll loop bandwidth f bw 1.0 mhz initial start-up time t start time from power-up to when the device gener- ates clocks (input fre- quency >48 mhz) 30 45 ms pll lock time 1 t acq f in = 19.44 mhz 15 150 ms output delay adjustment t delay_frac f vco = 14 ghz delay is controlled by the multisynth 0.28 ps t delay_int 71.4 ps t range 9.14 ns por 2 to serial interface ready t rdy 15 ms SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 25
parameter symbol test condition min typ max units jitter generation locked to ex- ternal clock 3 j gen integer mode 4 12 khz to 20 mhz 140 180 fs rms fractional/dco mode 5 12 khz to 20 mhz 160 210 fs rms j per derived from integrated phase noise 110 fs pk-pk j cc 180 fs pk j per n = 10,000 cycles integer or fractional mode 4, 5 . measured in the time do- main. performance is limi- ted by the noise floor of the equipment. 7400 fs pk-pk j cc 6700 fs pk jitter generation locked to ex- ternal xtal xtal frequency = 48 mhz j gen integer mode 4 12 khz to 20 mhz 90 140 fs rms fractional/dco mode 5 12 khz to 20 mhz 115 170 fs rms j per derived from integrated phase noise 110 fs pk-pk j cc 180 fs pk j per n = 10, 000 cycles integer or fractional mode. 4 , 5 measured in the time do- main. performance is limi- ted by the noise floor of the equipment. 7400 fs pk-pk j cc 6600 fs pk xtal frequency = 25 mhz j gen integer mode 4 12 khz to 20 mhz 115 140 fs rms fractional mode 5 12 khz to 20 mhz 140 190 fs rms notes: 1. pll lock time is measured by first letting the pll lock, then turning off the input clock, and then turning on the input clock. the time from the first edge of the input clock being re-applied until lol de-asserts is the pll lock time. 2. measured as time from valid v dd and v dd33 rails (90% of their value) to when the serial interface is ready to respond to com- mands. measured in spi 4-wire mode, with sclk @ 10 mhz. 3. jitter generation test conditions f in = 100 mhz, f out = 156.25 mhz lvpecl. 4. integer mode assumes that the output dividers (nn/nd) are configured with an integer value. 5. fractional and dco modes assume that the output dividers (nn/nd) are configured with a fractional value and the feedback divid- er is integer. SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 26
table 5.9. i 2 c timing specifications (scl,sda) parameter symbol test condition standard mode 100 kbps fast mode 400 kbps units min max min max scl clock frequency f scl 100 400 khz hold time (repeated) start condition t hd:sta 4.0 0.6 s low period of the scl clock t low 4.7 1.3 s high period of the scl clock t high 4.0 0.6 s set-up time for a repeated start condition t su:sta 4.7 0.6 s data hold time t hd:dat 100 100 ns data set-up time t su:dat 250 100 ns rise time of both sda and scl signals t r 1000 20 300 ns fall time of both sda and scl signals t f 300 300 ns set-up time for stop con- dition t su:sto 4.0 0.6 s bus free time between a stop and start condition t buf 4.7 1.3 s data valid time t vd:dat 3.45 0.9 s data valid acknowledge time t vd:ack 3.45 0.9 s SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 27
figure 5.1. i 2 c serial port timing standard and fast modes SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 28
table 5.10. spi timing specifications (4-wire) (v dd =1.8v 5%, v dda =3.3v 5%, t a = -40 to 85c) parameter symbol min typ max units sclk frequency f spi 20 mhz sclk duty cycle t dc 40 60 % sclk period t c 50 ns delay time, sclk fall to sdo active t d1 12.5 18 ns delay time, sclk fall to sdo t d2 10 15 ns delay time, csb rise to sdo tri-state t d3 10 15 ns setup time, csb to sclk t su1 5 ns hold time, csb to sclk rise t h1 5 ns setup time, sdi to sclk rise t su2 5 ns hold time, sdi to sclk rise t h2 5 ns delay time between chip selects (csb) t cs 2 t c sclk csb sdi sdo t su1 t d 1 t su 2 t d2 t c t cs t d 3 t h2 t h1 figure 5.2. 4-wire spi serial interface timing SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 29
table 5.11. spi timing specifications (3-wire) (v dd =1.8v 5%, v dda =3.3v 5%, t a = -40 to 85c) parameter symbol min typ max units sclk frequency f spi 20 mhz sclk duty cycle t dc 40 60 % sclk period t c 50 ns delay time, sclk fall to sdo turn-on t d1 12.5 20 ns delay time, sclk fall to sdo next-bit t d2 10 15 ns delay time, csb rise to sdo tri-state t d3 10 15 ns setup time, csb to sclk t su1 5 ns hold time, csb to sclk rise t h1 5 ns setup time, sdi to sclk rise t su2 5 ns hold time, sdi to sclk rise t h2 5 ns delay time between chip selects (csb) t cs 2 t c sclk csb sdio t su1 t d1 t su2 t d2 t c t cs t d3 t h2 t h1 figure 5.3. 3-wire spi serial interface timing SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 30
table 5.12. crystal specifications parameter symbol test condition min typ max units crystal frequency range f xtal full operating range. jitter per- formance may be reduced. 24.97 54.06 mhz range for best jitter. 48 54 mhz load capacitance c l 8 pf crystal drive level d l 200 w equivalent series resistance shunt capacitance r esr c o refer to the SI5341/40 family reference manual to determine esr and shunt ca- pacitance. note: 1. refer to the SI5341/40 family reference manual for recommended 48 to 54 mhz crystals. the SI5341/40 are designed to work with crystals that meet these specifications. table 5.13. thermal characteristics parameter symbol test condition 1 value units SI5341 - 64qfn thermal resistance junction to ambient ? ja still air 22 c/w air flow 1 m/s 19.4 air flow 2 m/s 18.3 thermal resistance junction to case ? jc 9.5 thermal resistance junction to board ? jb 9.4 jb 9.3 thermal resistance junction to top center jt 0.2 si5340 - 44qfn thermal resistance junction to ambient ? ja still air 22.3 c/w air flow 1 m/s 19.4 air flow 2 m/s 18.4 thermal resistance junction to case ? jc 10.9 thermal resistance junction to board ? jb 9.3 jb 9.2 thermal resistance junction to top center jt 0.23 note: 1. based on pcb dimension: 3 x 4.5 mm, pcb land/via under gnd pad: 36, number of cu layers: 4 SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 31
table 5.14. absolute maximum ratings 1, 2, 3, 4 parameter symbol test condition value units storage temperature range t stg -55 to +150 c dc supply voltage v dd -0.5 to 3.8 v v dda -0.5 to 3.8 v v ddo 5 -0.5 to 3.8 v input voltage range v i1 in0-in2, fb_in -0.85 to 3.8 v v i2 in_sel[1:0], rstb, oeb, syncb, i2c_sel, sdi, sclk, a0/csb, a1, sda/sdio, finc/ fdec -0.5 to 3.8 v v i3 xa/xb -0.5 to 2.7 v latch-up tolerance lu jesd78 compliant esd tolerance hbm 100 pf, 1.5 k 2.0 kv maximum junction temperature in operation t jct 125 c soldering temperature (pb-free profile) 5 t peak 260 c soldering temperature time at t peak (pb-free profile) 5 t p 20 to 40 sec notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 2. 64-qfn and 44-qfn packages are rohs-6 compliant. 3. moisture sensitivity level is msl2. for more packaging information, go to the silicon labs rohs information page . 4. the minimum voltage at these pins can be as low as C1.0 v when an ac input signal of 10 mhz or greater is applied. see table 5.3 input clock specifications on page 20 spec for single-ended ac-coupled f in < 250 mhz. 5. the device is compliant with jedec j-std-020. SI5341/40 rev d data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 32
6. typical application schematic xa xb 25 mhz traditional discrete clock tree level translator clock generator 161.1328125 mhz buffer 133.33 mhz buffer one SI5341 replaces: 3x crystal oscillators (xo) 2x buffers 1x clock generator 2x level translators 1x delay line clock tree on-a-chip xa xb 25 mhz 200 mhz 2.5v lvcmos 2x 161.1328125 mhz lvds 2x 133.33 mhz 1.8v lvcmos buffer 125 mhz level translator buffer delay line 4x 125 mhz 3.3v lvcmos 3x 125 mhz lvpecl SI5341 1x 161.1328125 mhz lvds 1x 161.1328125 mhz lvds 2x 133.33 mhz 1.8v lvcmos 2x 125 mhz 3.3v lvcmos 2x 125 mhz 3.3v lvcmos 2x 200 mhz 2.5v lvcmos 2x 200 mhz 2.5v lvcmos 1x 125 mhz lvpecl 1x 125 mhz lvpecl 1x 125 mhz lvpecl figure 6.1. using the SI5341 to replace a traditional clock tree SI5341/40 rev d data sheet typical application schematic silabs.com | smart. connected. energy-friendly. rev. 1.0 | 33
7. detailed block diagrams vdd vdda 3 sda/ sdio a1/ sdo sclk a0/csb i2c_ sel spi / i 2 c nvm rstb zero delay mode fb_in fb_ inb oeb SI5341 generator clock r 0 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 1 out0b vddo0 out0 out2b vddo2 out2 out3b vddo3 out3 out4b vddo4 out4 out5b vddo5 out5 out6b vddo6 out6 out7b vddo7 out7 out8b vddo8 out8 out9b vddo9 out9 out1b vddo1 out1 p fb lpf pd m n m d pll in_ sel[1:0] xa xb p 2 p 1 p 0 in0 in0b in1 in1b in2 in2b fdec finc frequency control n 0n n 0d t 0 n 2n n 2d n 3n n 3d n 4n n 4d t 2 t 3 t 4 n 1n n 1d t 1 multisynth syncb dividers/ drivers status monitors lo lb intrb osc p xaxb 25-54 mhz xtal figure 7.1. SI5341 block diagram SI5341/40 rev d data sheet detailed block diagrams silabs.com | smart. connected. energy-friendly. rev. 1.0 | 34
rstb oeb n n0 n d0 t 0 n 2n n 2d n 3n n 3d t 2 t 3 n n1 n d1 t 1 lpf pd pll m n m d lo lb i nt rb losxab sda/sdio a1/sdo sclk a0/csb i2c_sel spi / i 2 c nvm status monitors multisynth r 0 r 2 r 3 r 1 out0b vddo0 out0 out2b vddo2 out2 out3b vddo3 out3 out1b vddo1 out1 dividers/ drivers zero delay mode fb_in fb_inb p fb in_sel[1:0] p 2 p 1 p 0 in0 in0b in1 in1b in2 in2b xa xb 25-54 mhz xtal osc p si5340 generator clock vdd vdda 4 2 xaxb vdds 1 figure 7.2. si5340 detailed block diagram SI5341/40 rev d data sheet detailed block diagrams silabs.com | smart. connected. energy-friendly. rev. 1.0 | 35
8. typical operating characteristics figure 8.1. integer mode--48 mhz crystal, 625 mhz output (2.5 v lvds) SI5341/40 rev d data sheet typical operating characteristics silabs.com | smart. connected. energy-friendly. rev. 1.0 | 36
figure 8.2. integer mode--48 mhz crystal, 156.25 mhz output (2.5 v lvds) figure 8.3. fractional mode--48 mhz crystal, 155.52 mhz output (2.5 v lvds) SI5341/40 rev d data sheet typical operating characteristics silabs.com | smart. connected. energy-friendly. rev. 1.0 | 37
9. pin descriptions gnd pad in1 in1b in_ sel0 in_ sel1 syncb rstb x1 xa xb x2 oeb intrb vdda in2 in2b sclk a0/csb sda/sdio a1/sdo vdd rsvd rsvd vddo0 out0b out0 fdec out1b out1 vddo2 out2b out2 finc lolb vdd out 6 out6b vddo6 out5 out5b vddo 5 i2c_sel out4 out4b vddo4 out3 out3b vddo 3 vddo7 out7b out7 vddo8 out8b out8 out9b o u t9 vddo9 vdd fb_in fb_inb in0 in0b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vddo1 si 5341 64qfn top view rsvd rsvd gnd pad in 1 in1b in_ sel0 intrb x1 xa xb x2 oeb rstb vdda vdda in2 a0/csb sda/ sdio a1/sdo out0b out0 vddo0 sclk i2c_sel out1 out 1b vddo1 vddo3 out3b out3 fb_in fb_inb in0 in0b si 5340 44qfn t op view 1 2 3 4 5 6 7 8 9 10 33 32 31 30 29 28 27 26 25 24 12 13 14 15 16 17 18 19 20 21 44 43 42 41 40 39 38 37 36 35 vdd out2 out2b vddo2 vdds lolb los_xaxbb vdd in_sel1 in2b 1 1 23 nc 22 vdd vdd 34 SI5341/40 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 38
table 9.1. pin descriptions pin name pin number pin type 1 function SI5341 si5340 inputs xa 8 5 i crystal and external clock input. these pins are used to con- nect an external crystal or an external clock. see 3.3.1 xa/xb clock and crystal input and figure 3.2 xaxb external crystal and clock connections on page 5 for connection information. if in_sel[1:0] = 11b, then the xaxb input is selected. if the xaxb input is not used and powered down, then both inputs can be left unconnected. clockbuilder pro will power down an input that is set as "unused". xb 9 6 i x1 7 4 i xtal shield. connect these pins directly to the xtal ground pins. x1, x2, and the xtal ground pins must not be connected to the pcb ground plane. do not ground the crystal ground pins. refer to the SI5341/40 family reference manual for layout guidelines. these pins should be left disconnected when connecting xa/xb pins to an external reference clock. x2 10 7 i in0 63 43 i clock inputs. these pins accept both differential and single- ended clock signals. refer 3.3.2 input clocks (in0, in1, in2) for input termination options. these pins are high-impedance and must be terminated externally. if both the inx and inx (with over- strike) inputs are un-used and powered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "unused". in0b 64 44 i in1 1 1 i in1b 2 2 i in2 14 10 i in2b 15 11 i fb_in 61 41 i external feedback input. these pins are used as the external feedback input (fb_in/fb_inb) for the optional zero delay mode. see 3.5.12 zero delay mode for details on the optional zero delay mode. if fb_in and fb_in (with overstrike) are un-used and pow- ered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "unused". fb_inb 62 42 i SI5341/40 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 39
pin name pin number pin type 1 function SI5341 si5340 outputs out0 24 20 o output clocks. these output clocks support a programmable signal amplitude when configured as a differential output. desired output signal format is configurable using register control. termi- nation recommendations are provided in 3.5.2 differential output terminations and 3.5.4 lvcmos output terminations. unused outputs should be left unconnected. out0b 23 19 o out1 28 25 o out1b 27 24 o out2 31 31 o out2b 30 30 o out3 35 36 o out3b 34 35 o out4 38 o out4b 37 o out5 42 o out5b 41 o out6 45 o out6b 44 o out7 51 o out7b 50 o out8 54 o out8b 53 o out9 59 o out9b 58 o serial interface i2c_sel 39 38 i i 2 c select. 2 this pin selects the serial interface mode as i 2 c (i2c_sel = 1) or spi (i2c_sel = 0). this pin is internally pulled up by a ~ 20 k resistor to the voltage selected by the io_vdd_sel register bit. sda/sdio 18 13 i/o serial data interface. 2 this is the bidirectional data pin (sda) for the i 2 c mode, or the bidirectional data pin (sdio) in the 3-wire spi mode, or the input data pin (sdi) in 4-wire spi mode. when in i 2 c mode, this pin must be pulled-up using an external resistor of at least 1 k . no pull-up resistor is needed when in spi mode. a1/sdo 17 15 i/o address select 1/serial data output. 2 in i 2 c mode, this pin functions as the a1 address input pin and does not have an inter- nal pull up or pull down resistor. in 4-wire spi mode this is the se- rial data output (sdo) pin (sdo) pin and drives high to the volt- age selected by the io_vdd_sel pin. sclk 16 14 i serial clock input. 2 this pin functions as the serial clock input for both i 2 c and spi modes.this pin is internally pulled up by a ~20 k resistor to the voltage selected by the io_vdd_sel regis- ter bit. in i 2 c mode this pin should have an external pull up of at least 1 k . no pull-up resistor is needed when in spi mode. SI5341/40 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 40
pin name pin number pin type 1 function SI5341 si5340 a0/csb 19 16 i address select 0/chip select. 2 this pin functions as the hard- ware controlled address a0 in i 2 c mode. in spi mode, this pin functions as the chip select input (active low). this pin is internally pulled up by a ~20 k resistor to the voltage selected by the io_vdd_sel register bit. control/status intrb 12 33 o interrupt. 2 this pin is asserted low when a change in device sta- tus has occurred. this interrupt has a push pull output and should be left unconnected when not in use. rstb 6 17 i device reset. 2 active low input that performs power-on reset (por) of the device. resets all internal logic to a known state and forces the device registers to their default values. clock outputs are disabled during reset. this pin is internally pulled up with a ~20 k resistor to the voltage selected by the io_vdd_sel bit. oeb 11 12 i output enable. 2 this pin disables all outputs when held high. this pin is internally pulled low and can be left unconnected when not in use. lolb 47 o loss of lock. 2 this output pin indicates when the dspll ? is locked (high) or out-of-lock (low). an external pull up or pull down is not needed. 27 o loss of lock. 3 this output pin indicates when the dspll is locked (high) or out-of-lock (low). an external pull up or pull down is not needed. los_xaxbb 28 o loss of signal. 3 this output pin indicates a loss of signal at the xa/xb pins. syncb 5 i output clock synchronization. 2 an active low signal on this pin resets the output dividers for the purpose of re-aligning the output clocks. for a tighter alignment of the clocks, a soft reset should be applied. this pin is internally pulled up with a ~20 k resistor to the voltage selected by the io_vdd_sel bit and can be left un- connected when not in use. fdec 25 i frequency decrement pin. 2 this pin is used to step-down the output frequency of a selected output. the affected output driver and its frequency change step size is register configurable. this pin is internally pulled low with a ~20 k resistor and can be left unconnected when not in use. finc 48 i frequency increment pin. 2 this pin is used to step-up the out- put frequency of a selected output. the affected output and its fre- quency change step size is register configurable. this pin is inter- nally pulled low with a ~20 k resistor and can be left unconnec- ted when not in use. in_sel0 3 3 i input reference select. 2 the in_sel[1:0] pins are used in the manual pin controlled mode to select the active clock input. these pins are internally pulled up with a ~20 k resistor to the voltage selected by the io_vdd_sel bit and can be left unconnected when not in use. in_sel1 4 37 i rsvd 20 reserved. these pins are connected to the die. leave discon- nected. 21 55 56 SI5341/40 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 41
pin name pin number pin type 1 function SI5341 si5340 nc 22 no connect. these pins are not connected to the die. leave dis- connected. power vdd 32 21 p core supply voltage. the device core operates from a 1.8 v supply. a 1.0 f bypass capacitor is recommended. 46 32 60 39 40 vdda 13 8 p core supply voltage 3.3 v. this core supply pin requires a 3.3 v power source. a 1.0 f bypass capacitor is recommended. 9 p vdds 26 p status output voltage. the voltage on this pin determines the v ol /v oh on lolb and los_xaxbb status output pins. a 0.1 f to 1.0 f bypass capacitor is recommended. vddo0 22 18 p output clock supply voltage 0C9. supply voltage (3.3 v, 2.5 v, 1.8 v) for outx, outx outputs. see the SI5341/40 family refer- ence manual for power supply filtering recommendations. leave vddo pins of unused output drivers unconnected. an alternate option is to connect the vddo pin to a power supply and disable the output driver to minimize current consumption. vddo1 26 23 p vddo2 29 29 p vddo3 33 34 p vddo4 36 p vddo5 40 p vddo6 43 p vddo7 49 p vddo8 52 p vddo9 57 p gnd pad p ground pad this pad provides electrical and thermal connection to ground and must be connected for proper operation. use as many vias as practical and keep the via length to an internal ground plan as short as possible. note: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1.8 v operation. 3. the voltage on the vdds pin(s) determines 3.3 v or 1.8 v operation. 4. refer to the family reference manual for more information on register setting names. 5. all status pins except i2c and spi are push-pull. SI5341/40 rev d data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 42
10. package outlines 10.1 SI5341 9x9 mm 64-qfn package diagram the figure below illustrates the package details for the SI5341. the table below lists the values for the dimensions shown in the illustra- tion. figure 10.1. 64-pin quad flat no-lead (qfn) table 10.1. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 9.00 bsc d2 5.10 5.20 5.30 e 0.50 bsc e 9.00 bsc e2 5.10 5.20 5.30 l 0.30 0.40 0.50 aaa 0.15 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5341/40 rev d data sheet package outlines silabs.com | smart. connected. energy-friendly. rev. 1.0 | 43
10.2 si5340 7x7 mm 44-qfn package diagram the figure below illustrates the package details for the si5340. the table below lists the values for the dimensions shown in the illustra- tion. figure 10.2. 44-pin quad flat no-lead (qfn) table 10.2. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 7.00 bsc d2 5.10 5.20 5.30 e 0.50 bsc e 7.00 bsc e2 5.10 5.20 5.30 l 0.30 0.40 0.50 aaa 0.15 bbb 0.10 ccc 0.08 ddd 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5341/40 rev d data sheet package outlines silabs.com | smart. connected. energy-friendly. rev. 1.0 | 44
11. pcb land pattern the figure below illlustrates the pcb land pattern details for the devices. the table below lists the values for the dimensions shown in the illustration. SI5341 si5340 figure 11.1. pcb land pattern SI5341/40 rev d data sheet pcb land pattern silabs.com | smart. connected. energy-friendly. rev. 1.0 | 45
table 11.1. pcb land pattern dimensions dimension SI5341 (max) si5340 (max) c1 8.90 6.90 c2 8.90 6.90 e 0.50 0.50 x1 0.30 0.30 y1 0.85 0.85 x2 5.30 5.30 y2 5.30 5.30 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). least material condition is calculated based on a fabrication allowance of 0.05 mm. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 33 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5341/40 rev d data sheet pcb land pattern silabs.com | smart. connected. energy-friendly. rev. 1.0 | 46
12. top marking tw yywwtttttt rx x x x x - gm si 5 3 4 1 g - e 4 tw yywwtttttt rx x x x x - gm si 5 3 4 0 g - e 4 64-qfn 44-qfn figure 12.1. SI5341-40 top markings table 12.1. SI5341-40 top marking explanation line characters description 1 SI5341g- si5340g- base part number and device grade for low jitter, any-frequency, 10-output clock generator. SI5341: 10-output, 64-qfn si5340: 4-output, 44-qfn g = device grade (a, b, c, d). see " " on page 26 for more information. C = dash character. 2 rxxxxx-gm r = product revision. (see ordering guide for current revision). xxxxx = customer specific nvm sequence number. optional nvm code assigned for custom, factory pre-programmed devices. characters are not included for standard, factory default configured devices. see or- dering guide for more information. Cgm = package (qfn) and temperature range (C40 to +85 c) 3 yywwtttttt yyww = characters correspond to the year (yy) and work week (ww) of package assembly. tttttt = manufacturing trace code. 4 circle w/ 1.6 mm (64-qfn) or 1.4 mm (44-qfn) diameter pin 1 indicator; left-justified e4 tw pb-free symbol; center-justified tw = taiwan; country of origin (iso abbreviation) SI5341/40 rev d data sheet top marking silabs.com | smart. connected. energy-friendly. rev. 1.0 | 47
13. device errata please log in or register at www.silabs.com to access the device errata document. SI5341/40 rev d data sheet device errata silabs.com | smart. connected. energy-friendly. rev. 1.0 | 48
14. document change list 14.1 revision 1.0 july 15, 2016 ? initial release. SI5341/40 rev d data sheet document change list silabs.com | smart. connected. energy-friendly. rev. 1.0 | 49
table of contents 1. features list ............................... 1 2. ordering guide ..............................2 3. functional description ............................4 3.1 power-up and initialization .........................4 3.2 frequency configuration ..........................4 3.3 inputs ................................4 3.3.1 xa/xb clock and crystal input .......................5 3.3.2 input clocks (in0, in1, in2) ........................6 3.3.3 input selection (in0, in1, in2, xa/xb) .....................7 3.4 fault monitoring .............................7 3.4.1 status indicators ............................7 3.4.2 interrupt pin (intrb) ...........................7 3.5 outputs ................................8 3.5.1 output signal format ...........................8 3.5.2 differential output terminations .......................8 3.5.3 programmable common mode voltage for differential outputs .............8 3.5.4 lvcmos output terminations .......................9 3.5.5 lvcmos output impedance and drive strength selection ..............9 3.5.6 lvcmos output signal swing .......................9 3.5.7 lvcmos output polarity .........................9 3.5.8 output enable/disable ..........................9 3.5.9 output driver state when disabled ......................9 3.5.10 synchronous/asynchronous output disable feature ................ 10 3.5.11 output delay control ( t 0 - t 4 ) ........................ 10 3.5.12 zero delay mode ............................ 11 3.5.13 sync pin (synchronizing r dividers) ..................... 11 3.5.14 output crosspoint ........................... 11 3.5.15 digitally controlled oscillator (dco) modes ................... 12 3.5.15.1 dco with frequency increment/decrement pins/bits ............... 12 3.5.15.2 dco with direct register writes ...................... 12 3.6 power management ............................ 12 3.7 in-circuit programming ........................... 12 3.8 serial interface ............................. 12 3.9 custom factory preprogrammed devices .................... 12 3.10 enabling features and/or configuration settings not available in clockbuilder pro for factory pre- programmed devices ........................... 13 4. register map .............................. 15 4.1 addressing scheme ............................ 15 4.2 high-level register map .......................... 16 5. electrical specifications .......................... 18 6. typical application schematic ........................ 33 table of contents 50
7. detailed block diagrams .......................... 34 8. typical operating characteristics ...................... 36 9. pin descriptions ............................. 38 10. package outlines ............................ 43 10.1 SI5341 9x9 mm 64-qfn package diagram ................... 43 10.2 si5340 7x7 mm 44-qfn package diagram ................... 44 11. pcb land pattern ............................ 45 12. top marking .............................. 47 13. device errata .............................. 48 14. document change list .......................... 49 14.1 revision 1.0 .............................. 49 table of contents 51
http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa clockbuilder pro one-click access to timing tools, documentation, software, source code libraries & more. available for windows and ios (cbgo only). www.silabs.com/cbpro timing portfolio www.silabs.com/timing sw/hw www.silabs.com/cbpro quality www.silabs.com/quality support and community community.silabs.com disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products are not designed or authorized to be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are not designed or authorized for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc.? , silicon laboratories?, silicon labs?, silabs? and the silicon labs logo?, bluegiga?, bluegiga logo?, clockbuilder?, cmems?, dspll?, efm?, efm32?, efr, ember?, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezradio?, ezradiopro?, gecko?, isomodem?, precision32?, proslic?, simplicity studio?, siphy?, telegesis, the telegesis logo?, usbxpress? and others are trademarks or registered trademarks of silicon laborato - ries inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders.

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